FIG. 1A shows a prior art protocol for acknowledging wireless packets on a per-packet basis. A wireless access point shown as AP1 102 transmits a first packet PKT1 106, which the wireless receiving station STA1 104 receives and acknowledges with an acknowledgement packet ACK1 108. The access point AP1 102 similarly sends additional packets PKT2, PKT3, PKT4, and PKT5, each of which is respectively acknowledged by ACK2, ACK3, ACK4, and ACK5. If a particular packet is not received or acknowledged such as PKT6 114, it is retransmitted 116 after an interval of time until it is acknowledged 118.
FIG. 1B shows a prior art block acknowledgement transmission protocol, whereby access point AP1 130 transmits a block of packets PKT1 through PKT6 134, along with a block acknowledgement request 136 which identifies the packets transmitted. If all packets were received, the station 132 sends a single acknowledgement 138 for the received packets PKT1 through PKT6. FIG. 1C shows a prior art block acknowledgement where packets 2 and 4 are not received. AP1 150 sends packets PKT1 through PKT6 154, along with block acknowledgement request 156. The station STA1 152 then acknowledges receipt of packets 1, 3, and 5-6. AP1 150 responds by re-transmitting packets 2 160 and 4 162 with a new block acknowledgement request 164 for retransmitted packets 2 and 4, which are later acknowledged 166.
FIG. 2A shows a block diagram for a prior art block acknowledgement processor 200. Packets to be transmitted are in the form of payload data stored in the host memory 204, which is typically external memory and coupled to a CPU 208 via a memory controller (not shown). The Central Processing Unit (CPU) 208 reads the payload data from host memory 204 and writes a particular block to be transmitted to the packet buffer 202, organizing the data in the packet buffer 202 by arrangement as payload data for each individual packet to be transmitted, shown as pkt1 through pkt 7 205. A Media Access Controller (MAC) 206 reads the packet data, one packet at a time, and forms a frame including a MAC (layer two) source and destination address, other header information, and a CRC (Cyclic Redundancy Check) as is known in the art of packet processing. The resulting data to be transmitted is transferred from host memory 204 and buffered into packet buffer 202, shown as pkt1 . . . pkt7. Optionally, the packet contents may be encrypted using the encryption engine 207 such as a packet at a time shown as epkt1 209, after which the baseband processor 210 performs digital processing and encoding necessary to provide a baseband signal suitable for modulation to a carrier frequency by the PHY 212, amplification 214, and transmission to the antenna 216.
FIG. 2B shows the prior art transmit process 250 performed by the CPU 208 and MAC 206 of FIG. 2A, whereby the CPU moves the data such as pkt1 through pkt7 from host memory to packet buffer in step 254, and the packets are successively transmitted 256 followed by the transmission of a block acknowledgement request 258 which includes identification of the packets transmitted in step 256. If an acknowledgement 260 is received from the remote station with all packets indicated as received, the process ends in step 266. If missing packets are detected, only the missing packets are transferred from host memory to packet memory 261, re-transmitted 262, which optionally includes re-encryption for encrypted packets, and a new acknowledgement request 214 is sent. An acknowledgement is subsequently received in step 260, either indicating all packets have been received, or providing a list of packets yet to be received.
FIG. 2C shows the arrangement of data in the packet buffer 202 of FIG. 2C, which may be an on-chip part of the MAC 206. The memory buffer 202 is divided into discrete units, each of which contains payload data for a particular packet which have been transferred from host memory 204. In one version of the prior art, when packets are not received by a station, such as packets 2 and 4 as shown 204, the packet buffer contents remain along with the previously sent packets, as shown in FIG. 2D, until the missing packets 204 are successfully transmitted, after which the packet buffer may be fully overwritten with the new packet buffer contents for the next block. During the interval of time awaiting confirmation of receipt of the block of data which includes the lost packets, the on-chip memory 202 is unavailable for any other purpose, such that for the example of a 7 packet transmission, for which 2 were lost, the received 5 packets remain in the buffer until the retransmitted two packets are acknowledged. In another version of the prior art, the host memory is used for temporary storage of transmitted packets until acknowledgement, which requires CPU bandwidth resources and MAC bandwidth and memory resources to re-transfer the missing packets from the host memory to packet buffer memory. If the lost packet requires encryption, the replacement packet it typically re-encrypted, requiring additional encryption resources.
One problem of the prior art block acknowledgement processors is that the packet buffer 202 remains filled with previously-sent packets, and remains unusable for a block of new packets until the missing packets of the previous block are transmitted and acknowledged.
Another problem of the prior art block acknowledgement processor is that computationally intensive operations, such as the encryption performed by processor 207, must be performed each time a packet is to be re-transmitted.